1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to an improvement in access time of a semiconductor memory device.
2. Description of the Background Art
Static RAMs (Random Access Memory), dynamic RAMs, EP-ROMs (Erasable Programmable Read Only Memory), mask ROMs, etc. are known as semiconductor memory devices. Increase in memory capacity and reduction in access time are the most desired features in such semiconductor memory devices. This is because the performance of electronic equipment incorporating the semiconductor memory device is mainly determined by the memory capacity and access time thereof.
Advanced processing techniques that can minimize the width of the patterned conductor line is necessary for increasing memory capacity. Also, processing techniques for forming silicide gates and double-layered aluminum wirings of field effect transistors, for example, are necessary to decrease resistivity of inner wiring for reducing access time. In recent years, ATD (Address Transition Detector) circuits have been employed in semiconductor memory devices to reduce access time by improvement in circuit design. An ATD circuit senses an address input signal to generate a pulse signal. The pulse signal provided from the ATD circuit operates dynamically the inner circuitry of the semiconductor memory device, resulting in reduction in access time. An example of a dynamic operation of a static RAM will be explained hereinafter.
FIG. 5 is a block diagram showing an example of a static RAM according to prior art. Referring to the semiconductor memory device of FIG. 5, external address signals 1.sub.l-1.sub.n pass an address buffer 2 to drive a word line selection decoder 3 and a bit line selection decoder 4. Word line selection decoder 3 selects one of word lines 6.sub.l-6.sub.n, to which a signal of H (high) level is applied. Memory cells 5.sub.l -5.sub.n are connected to word lines 6.sub.l -6.sub.n, respectively. A memory cell connected to the selected word line provides an information signal of H (high) level or L (low) level to BIT lines 9a.sub.l -9a.sub.n and BIT lines 9b.sub.l -9b.sub.n.
In response to the output signal of bit line selection decoder 4, a bit line selection circuit 8 selects a desired bit line pair out of BIT lines 9a.sub.l -9a.sub.n and BIT lines 9b.sub.l -9b.sub.n, whereby the signal of the selected bit line pair is provided to a sense amplifier 13. Sense amplifier 13 amplifies the signal level of the information signal. This amplified information signal is applied to an output buffer 14, whereby an H level or L level representing the information signal appears at external output terminals 15.sub.l -15.sub.n.
An ATD circuit 11 receives a signal from address buffer 2 to provide a predetermined pulse signal on output line 12 in synchronization with the rise and fall of external address input signal 1.sub.l -1.sub.n. The output 12 of ATD circuit 11 controls the ON/OFF of a switching transistor 10 between BIT lines 9a.sub.l -9a.sub.n and BIT lines 9b.sub.l -9b.sub.n. The output of the ATD circuit also functions to equalize the signal line between bit line selection circuit 8 and sense amplifier 13, sense amplifier 13 itself, and the signal line between sense amplifier 13 and output buffer 14 to a desirable potential.
FIG. 6 shows several examples of signal waveforms of the static RAM of FIG. 5 in comparison with signal waveforms of a static RAM that does not have an ATD circuit. In a static RAM not having an ATD circuit, a word line signal B1 rises after address input signal A1 rises. When word line signal B1 rises, bit line pair signal D1 is provided.
In a static RAM having an ATD circuit, word line signal B2 rises after the rise of address input signal A2. Also, an ATD pulse C2 is generated in response to the rise or fall of address input signal A2. Because ATD pulse C2 turns on switching transistor 10 of FIG. 5 to make a short circuit between the BIT line and the BIT line, BIT line and BIT line are equalized to an intermediate level (refer to bit line pair signal D2) during the duration period of ATD pulse C2. After ATD pulse C2 attains an L level to turn off switching transistor 10, signal B2 on the selected word line attains an H level. Accordingly, an information signal of H or L is provided from the memory cell connected to the selected word line onto the bit line pair. Because the BIT line and the BIT line change to an H level or an L level from the intermediate level at this time, the access time is reduced by time in comparison with the static RAM not having an ATD circuit where the BIT line and the BIT line changes from an L to H level, or from an H to L level.
Similarly, the signal line between bit line selection circuit 8 and sense amplifier 13, the sense amplifier 13 itself, and the signal line between sense amplifier 13 and output buffer 14 are equalized to the intermediate level only during the duration period of ATD pulse C2, resulting in further reduction in access time. The equalization of the sense amplifier itself is described in Digest of Technical Papers of IEEE International Solid-State Circuit Conference, 1984, pp. 222-223 by Minato, et al., for example.
In the static RAM of FIG. 5 according to the prior art, it is necessary to limit the duration period of ATD pulse C2 to be within a time period range from the rise of address signal A2 to the rise of signal B2 of the selected word line. This is because if ATD pulse C2 is still maintained even after word line signal B2 rises, BIT line and BIT line cannot be isolated into an H level and an L level, resulting in increase in access time due to ATD pulse C2.
Since ATD circuit 11 comprises a transistor logic, a capacitor and the like, the duration period of ATD pulse C2 is liable to change due to variation in channel width and threshold voltage of the transistor. Therefore, there was a problem that the access time is increased when the duration time of ATD pulse C2 provided from ATD circuit 11 is long.